Anshorei
/
epd-waveshare
mirror of https://github.com/Anshorei/epd-waveshare
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

epd7in5 HD: Rename Command enums for Clippy check

main
pi 2021-04-15 10:20:52 +01:00
parent a1e9c17b53
commit 989a236fb1
2 changed files with 66 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

86
src/epd7in5_hd/command.rs
View File

@ -11,131 +11,131 @@ use crate::traits;
#[allow(non_camel_case_types)] #[allow(non_camel_case_types)]
#[derive(Copy, Clone)] #[derive(Copy, Clone)]
pub(crate) enum Command { pub(crate) enum Command {
DRIVER_OUTPUT_CONTROL = 0x01, DriverOutputControl = 0x01,
/// Set gate driving voltage /// Set gate driving voltage
GATE_DRIVING_VOLTAGE_CONTROL = 0x03, GateDrivingVoltageControl = 0x03,
/// Set source driving voltage /// Set source driving voltage
SOURCE_DRIVING_VOLTAGE_CONTROL = 0x04, SourceDrivingVoltageControl = 0x04,
SOFT_START = 0x0C, SoftStart = 0x0C,
/// Set the scanning start position of the gate driver. /// Set the scanning start position of the gate driver.
/// The valid range is from 0 to 679. /// The valid range is from 0 to 679.
GATE_SCAN_START_POSITION = 0x0F, GateScanStartPosition = 0x0F,
/// Deep sleep mode control /// Deep sleep mode control
DEEP_SLEEP = 0x10, DeepSleep = 0x10,
/// Define data entry sequence /// Define data entry sequence
DATA_ENTRY = 0x11, DataEntry = 0x11,
/// resets the commands and parameters to their S/W Reset default values except R10h-Deep Sleep Mode. /// resets the commands and parameters to their S/W Reset default values except R10h-Deep Sleep Mode.
/// During operation, BUSY pad will output high. /// During operation, BUSY pad will output high.
/// Note: RAM are unaffected by this command. /// Note: RAM are unaffected by this command.
SW_RESET = 0x12, SwReset = 0x12,
/// After this command initiated, HV Ready detection starts. /// After this command initiated, HV Ready detection starts.
/// BUSY pad will output high during detection. /// BUSY pad will output high during detection.
/// The detection result can be read from the Status Bit Read (Command 0x2F). /// The detection result can be read from the Status Bit Read (Command 0x2F).
HV_READY_DETECTION = 0x14, HvReadyDetection = 0x14,
/// After this command initiated, VCI detection starts. /// After this command initiated, VCI detection starts.
/// BUSY pad will output high during detection. /// BUSY pad will output high during detection.
/// The detection result can be read from the Status Bit Read (Command 0x2F). /// The detection result can be read from the Status Bit Read (Command 0x2F).
VCI_DETECTION = 0x15, VciDetection = 0x15,
/// Temperature Sensor Selection /// Temperature Sensor Selection
TEMPERATURE_SENSOR_CONTROL = 0x18, TemperatureSensorControl = 0x18,
/// Write to temperature register /// Write to temperature register
TEMPERATURE_SENSOR_WRITE = 0x1A, TemperatureSensorWrite = 0x1A,
/// Read from temperature register /// Read from temperature register
TEMPERATURE_SENSOR_READ = 0x1B, TemperatureSensorRead = 0x1B,
/// Write Command to External temperature sensor. /// Write Command to External temperature sensor.
TEMPERATURE_SENSOR_WRITE_EXTERNAL = 0x1C, TemperatureSensorWriteExternal = 0x1C,
/// Activate Display Update Sequence /// Activate Display Update Sequence
MASTER_ACTIVATION = 0x20, MasterActivation = 0x20,
/// RAM content option for Display Update /// RAM content option for Display Update
DISPLAY_UPDATE_CONTROL_1 = 0x21, DisplayUpdateControl1 = 0x21,
/// Display Update Sequence Option /// Display Update Sequence Option
DISPLAY_UPDATE_CONTROL_2 = 0x22, DisplayUpdateControl2 = 0x22,
/// After this command, data entries will be written into the BW RAM until another command is written /// After this command, data entries will be written into the BW RAM until another command is written
WRITE_RAM_BW = 0x24, WriteRamBw = 0x24,
/// After this command, data entries will be written into the RED RAM until another command is written /// After this command, data entries will be written into the RED RAM until another command is written
WRITE_RAM_RED = 0x26, WriteRamRed = 0x26,
/// Fetch data from RAM /// Fetch data from RAM
READ_RAM = 0x27, ReadRam = 0x27,
/// Enter VCOM sensing conditions /// Enter VCOM sensing conditions
VCOM_SENSE = 0x28, VcomSense = 0x28,
/// Enter VCOM sensing conditions /// Enter VCOM sensing conditions
VCOM_SENSE_DURATION = 0x29, VcomSenseDuration = 0x29,
/// Program VCOM register into OTP /// Program VCOM register into OTP
VCOM_PROGRAM_OTP = 0x2A, VcomProgramOtp = 0x2A,
/// Reduces a glitch when ACVCOM is toggled /// Reduces a glitch when ACVCOM is toggled
VCOM_CONTROL = 0x2B, VcomControl = 0x2B,
/// Write VCOM register from MCU interface /// Write VCOM register from MCU interface
VCOM_WRITE = 0x2C, VcomWrite = 0x2C,
/// Read Register for Display Option /// Read Register for Display Option
OTP_READ = 0x2D, OtpRead = 0x2D,
/// CRC calculation command for OTP content validation /// CRC calculation command for OTP content validation
CRC_CALCULATION = 0x34, CrcCalculation = 0x34,
/// CRC Status Read /// CRC Status Read
CRC_READ = 0x35, CrcRead = 0x35,
/// Program OTP Selection according to the OTP Selection Control /// Program OTP Selection according to the OTP Selection Control
PROGRAM_SELECTION = 0x36, ProgramSelection = 0x36,
/// Write Register for Display Option /// Write Register for Display Option
DISPLAY_OPTION_WRITE = 0x37, DisplayOptionWrite = 0x37,
/// Write register for User ID /// Write register for User ID
USER_ID_WRITE = 0x38, UserIdWrite = 0x38,
/// Select border waveform for VBD /// Select border waveform for VBD
VBD_CONTROL = 0x3C, VbdControl = 0x3C,
/// Read RAM Option /// Read RAM Option
READ_RAM_OPTION = 0x41, ReadRamOption = 0x41,
/// Specify the start/end positions of the window address in the X direction by an address unit for RAM /// Specify the start/end positions of the window address in the X direction by an address unit for RAM
SET_RAM_X_START_END = 0x44, SetRamXStartEnd = 0x44,
/// Specify the start/end positions of the window address in the Y direction by an address unit for RAM /// Specify the start/end positions of the window address in the Y direction by an address unit for RAM
SET_RAM_Y_START_END = 0x45, SetRamYStartEnd = 0x45,
/// Auto write RED RAM for regular pattern /// Auto write RED RAM for regular pattern
AUTO_WRITE_RED = 0x46, AutoWriteRed = 0x46,
/// Auto write B/W RAM for regular pattern /// Auto write B/W RAM for regular pattern
AUTO_WRITE_BW = 0x47, AutoWriteBw = 0x47,
/// Make initial settings for the RAM X address in the address counter (AC) /// Make initial settings for the RAM X address in the address counter (AC)
SET_RAM_X_AC = 0x4E, SetRamXAc = 0x4E,
/// Make initial settings for the RAM Y address in the address counter (AC) /// Make initial settings for the RAM Y address in the address counter (AC)
SET_RAM_Y_AC = 0x4F, SetRamYAc = 0x4F,
/// This command is an empty command; it does not have any effect on the display module. /// This command is an empty command; it does not have any effect on the display module.
/// However, it can be used to terminate Frame Memory Write or Read Commands. /// However, it can be used to terminate Frame Memory Write or Read Commands.
NOP = 0x7F, Nop = 0x7F,
} }
impl traits::Command for Command { impl traits::Command for Command {
@ -152,8 +152,8 @@ mod tests {
#[test] #[test]
fn command_addr() { fn command_addr() {
assert_eq!(Command::MASTER_ACTIVATION.address(), 0x20); assert_eq!(Command::MasterActivation.address(), 0x20);
assert_eq!(Command::SW_RESET.address(), 0x12); assert_eq!(Command::SwReset.address(), 0x12);
assert_eq!(Command::DISPLAY_UPDATE_CONTROL_2.address(), 0x22); assert_eq!(Command::DisplayUpdateControl2.address(), 0x22);
} }
} }

46
src/epd7in5_hd/mod.rs
View File

@ -66,34 +66,34 @@ where
// https://www.waveshare.com/w/upload/2/27/7inch_HD_e-Paper_Specification.pdf // https://www.waveshare.com/w/upload/2/27/7inch_HD_e-Paper_Specification.pdf
self.wait_until_idle(); self.wait_until_idle();
self.command(spi, Command::SW_RESET)?; self.command(spi, Command::SwReset)?;
self.wait_until_idle(); self.wait_until_idle();
self.cmd_with_data(spi, Command::AUTO_WRITE_RED, &[0xF7])?; self.cmd_with_data(spi, Command::AutoWriteRed, &[0xF7])?;
self.wait_until_idle(); self.wait_until_idle();
self.cmd_with_data(spi, Command::AUTO_WRITE_BW, &[0xF7])?; self.cmd_with_data(spi, Command::AutoWriteBw, &[0xF7])?;
self.wait_until_idle(); self.wait_until_idle();
self.cmd_with_data(spi, Command::SOFT_START, &[0xAE, 0xC7, 0xC3, 0xC0, 0x40])?; self.cmd_with_data(spi, Command::SoftStart, &[0xAE, 0xC7, 0xC3, 0xC0, 0x40])?;
self.cmd_with_data(spi, Command::DRIVER_OUTPUT_CONTROL, &[0xAF, 0x02, 0x01])?; self.cmd_with_data(spi, Command::DriverOutputControl, &[0xAF, 0x02, 0x01])?;
self.cmd_with_data(spi, Command::DATA_ENTRY, &[0x01])?; self.cmd_with_data(spi, Command::DataEntry, &[0x01])?;
self.cmd_with_data(spi, Command::SET_RAM_X_START_END, &[0x00, 0x00, 0x6F, 0x03])?; self.cmd_with_data(spi, Command::SetRamXStartEnd, &[0x00, 0x00, 0x6F, 0x03])?;
self.cmd_with_data(spi, Command::SET_RAM_Y_START_END, &[0xAF, 0x02, 0x00, 0x00])?; self.cmd_with_data(spi, Command::SetRamYStartEnd, &[0xAF, 0x02, 0x00, 0x00])?;
self.cmd_with_data(spi, Command::VBD_CONTROL, &[0x05])?; self.cmd_with_data(spi, Command::VbdControl, &[0x05])?;
self.cmd_with_data(spi, Command::TEMPERATURE_SENSOR_CONTROL, &[0x80])?; self.cmd_with_data(spi, Command::TemperatureSensorControl, &[0x80])?;
self.cmd_with_data(spi, Command::DISPLAY_UPDATE_CONTROL_2, &[0xB1])?; self.cmd_with_data(spi, Command::DisplayUpdateControl2, &[0xB1])?;
self.command(spi, Command::MASTER_ACTIVATION)?; self.command(spi, Command::MasterActivation)?;
self.wait_until_idle(); self.wait_until_idle();
self.cmd_with_data(spi, Command::SET_RAM_X_AC, &[0x00, 0x00])?; self.cmd_with_data(spi, Command::SetRamXAc, &[0x00, 0x00])?;
self.cmd_with_data(spi, Command::SET_RAM_Y_AC, &[0x00, 0x00])?; self.cmd_with_data(spi, Command::SetRamYAc, &[0x00, 0x00])?;
Ok(()) Ok(())
} }
@ -137,15 +137,15 @@ where
fn sleep(&mut self, spi: &mut SPI) -> Result<(), SPI::Error> { fn sleep(&mut self, spi: &mut SPI) -> Result<(), SPI::Error> {
self.wait_until_idle(); self.wait_until_idle();
self.cmd_with_data(spi, Command::DEEP_SLEEP, &[0x01])?; self.cmd_with_data(spi, Command::DeepSleep, &[0x01])?;
Ok(()) Ok(())
} }
fn update_frame(&mut self, spi: &mut SPI, buffer: &[u8]) -> Result<(), SPI::Error> { fn update_frame(&mut self, spi: &mut SPI, buffer: &[u8]) -> Result<(), SPI::Error> {
self.wait_until_idle(); self.wait_until_idle();
self.cmd_with_data(spi, Command::SET_RAM_Y_AC, &[0x00, 0x00])?; self.cmd_with_data(spi, Command::SetRamYAc, &[0x00, 0x00])?;
self.cmd_with_data(spi, Command::WRITE_RAM_BW, buffer)?; self.cmd_with_data(spi, Command::WriteRamBw, buffer)?;
self.cmd_with_data(spi, Command::DISPLAY_UPDATE_CONTROL_2, &[0xF7])?; self.cmd_with_data(spi, Command::DisplayUpdateControl2, &[0xF7])?;
Ok(()) Ok(())
} }
@ -162,7 +162,7 @@ where
} }
fn display_frame(&mut self, spi: &mut SPI) -> Result<(), SPI::Error> { fn display_frame(&mut self, spi: &mut SPI) -> Result<(), SPI::Error> {
self.command(spi, Command::MASTER_ACTIVATION)?; self.command(spi, Command::MasterActivation)?;
self.wait_until_idle(); self.wait_until_idle();
Ok(()) Ok(())
} }
@ -178,16 +178,16 @@ where
let background_color_byte = self.color.get_byte_value(); let background_color_byte = self.color.get_byte_value();
self.wait_until_idle(); self.wait_until_idle();
self.cmd_with_data(spi, Command::SET_RAM_Y_AC, &[0x00, 0x00])?; self.cmd_with_data(spi, Command::SetRamYAc, &[0x00, 0x00])?;
for cmd in &[Command::WRITE_RAM_BW, Command::WRITE_RAM_RED] { for cmd in &[Command::WriteRamBw, Command::WriteRamRed] {
self.command(spi, *cmd)?; self.command(spi, *cmd)?;
self.interface self.interface
.data_x_times(spi, background_color_byte, pixel_count)?; .data_x_times(spi, background_color_byte, pixel_count)?;
} }
self.cmd_with_data(spi, Command::DISPLAY_UPDATE_CONTROL_2, &[0xF7])?; self.cmd_with_data(spi, Command::DisplayUpdateControl2, &[0xF7])?;
self.command(spi, Command::MASTER_ACTIVATION)?; self.command(spi, Command::MasterActivation)?;
self.wait_until_idle(); self.wait_until_idle();
Ok(()) Ok(())
} }