Chris
7 years ago
5 changed files with 0 additions and 235 deletions
@ -1,2 +0,0 @@ |
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[build] |
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#rustflags = ["-Aproc-macro-derive-resolution-fallback"] |
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@ -1,18 +0,0 @@ |
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target remote :3333 |
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monitor arm semihosting enable |
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# # send captured ITM to the file itm.fifo |
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# # (the microcontroller SWO pin must be connected to the programmer SWO pin) |
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# # 8000000 must match the core clock frequency |
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# monitor tpiu config internal itm.fifo uart off 64000000 |
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# # OR: make the microcontroller SWO pin output compatible with UART (8N1) |
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# # 2000000 is the frequency of the SWO pin |
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# monitor tpiu config external uart off 64000000 2000000 |
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# # enable ITM port 0 |
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# monitor itm port 0 on |
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load |
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step |
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@ -1,22 +0,0 @@ |
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[package] |
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name = "stm32_f3_discovery_eink_example" |
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version = "0.1.0" |
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authors = ["Christoph Groß <christoph-gross@mailbox.org>"] |
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[dependencies] |
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#eink_waveshare_rs = { git = "https://github.com/Caemor/eink-waveshare-rs"} |
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#eink_waveshare_rs = { path = "../../"} |
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eink_waveshare_rs = { path = "../../", default-features = false, features = ["epd1in54"]} |
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#TODO: Update to the normal hal (either completly the f3 for the discovery or just stm3230x-hal) when PRs for InputPin are included |
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stm32f30x-hal = { git = "https://github.com/droogmic/stm32f30x-hal", features = ["unproven"]} |
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embedded-hal = { version = "0.2.1", features = ["unproven"] } |
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aligned = "0.2.0" |
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cortex-m = "0.5.7" |
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cortex-m-rt = "0.6.3" |
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cortex-m-semihosting = "0.3.1" |
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madgwick = "0.1.1" |
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panic-semihosting = "0.5.0" |
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@ -1,190 +0,0 @@ |
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//! Example for EInk-Waveshare and STM32F3
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#![deny(unsafe_code)] |
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#![no_main] |
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#![no_std] |
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//#![deny(warnings)]
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extern crate cortex_m_rt as rt; |
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extern crate cortex_m; |
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extern crate stm32f30x_hal; |
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extern crate panic_semihosting; |
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use rt::*; |
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//use cortex_m::asm;
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use stm32f30x_hal::prelude::*; |
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use stm32f30x_hal::spi::Spi; |
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use stm32f30x_hal::stm32f30x; |
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use stm32f30x_hal::delay::Delay; |
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use rt::ExceptionFrame; |
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//entry!(main);
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// the eink library
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extern crate eink_waveshare_rs; |
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use eink_waveshare_rs::{ |
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epd1in54::EPD1in54, |
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SPI_MODE, |
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//drawing_old::{Graphics},
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prelude::*, |
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}; |
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// use lin_hal::spidev::{self, SpidevOptions};
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// use lin_hal::{Pin, Spidev};
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// use lin_hal::sysfs_gpio::Direction;
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// use lin_hal::Delay;
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// activate spi, gpio in raspi-config
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// needs to be run with sudo because of some sysfs_gpio permission problems and follow-up timing problems
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// see https://github.com/rust-embedded/rust-sysfs-gpio/issues/5 and follow-up issues
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/* |
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* |
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* BE CAREFUL: this wasn't tested yet, and the pins are also not choosen correctly (just some random ones atm) |
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* |
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*/ |
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#[entry] |
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fn main() -> ! { |
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let cp = cortex_m::Peripherals::take().unwrap(); |
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let p = stm32f30x::Peripherals::take().unwrap(); |
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let mut flash = p.FLASH.constrain(); |
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let mut rcc = p.RCC.constrain(); |
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// clock configuration using the default settings (all clocks run at 8 MHz)
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let clocks = rcc.cfgr.freeze(&mut flash.acr); |
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// TRY this alternate clock configuration (all clocks run at 16 MHz)
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// let clocks = rcc.cfgr.sysclk(16.mhz()).freeze(&mut flash.acr);
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let mut gpioa = p.GPIOA.split(&mut rcc.ahb); |
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let mut gpioe = p.GPIOE.split(&mut rcc.ahb); |
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// // Configure Digital I/O Pin to be used as Chip Select for SPI
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let mut cs = gpioe |
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.pe3 |
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.into_push_pull_output(&mut gpioe.moder, &mut gpioe.otyper); |
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cs.set_high(); |
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// // Configure Busy Input Pin
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let busy = gpioe |
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.pe4 |
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.into_floating_input(&mut gpioe.moder, &mut gpioe.pupdr); |
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// .pe4
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// .into_push_pull_output(&mut gpioe.moder, &mut gpioe.otyper);
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// let busy = Pin::new(5);//pin 29
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// busy.export().expect("busy export");
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// while !busy.is_exported() {}
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// busy.set_direction(Direction::In).expect("busy Direction");
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// //busy.set_value(1).expect("busy Value set to 1");
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// let busy_in = HackInputPin::new(&busy);
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// // Configure Data/Command OutputPin
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let mut dc = gpioe |
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.pe5 |
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.into_push_pull_output(&mut gpioe.moder, &mut gpioe.otyper); |
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dc.set_high(); |
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// let dc = Pin::new(6); //pin 31 //bcm6
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// dc.export().expect("dc export");
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// while !dc.is_exported() {}
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// dc.set_direction(Direction::Out).expect("dc Direction");
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// dc.set_value(1).expect("dc Value set to 1");
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let mut rst = gpioe |
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.pe6 |
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.into_push_pull_output(&mut gpioe.moder, &mut gpioe.otyper); |
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rst.set_high(); |
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// // Configure Reset OutputPin
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// let rst = Pin::new(16); //pin 36 //bcm16
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// rst.export().expect("rst export");
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// while !rst.is_exported() {}
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// rst.set_direction(Direction::Out).expect("rst Direction");
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// rst.set_value(1).expect("rst Value set to 1");
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// // Configure Delay
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let mut delay = Delay::new(cp.SYST, clocks); |
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// copied from the l3gd20 example
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// The `L3gd20` abstraction exposed by the `f3` crate requires a specific pin configuration to
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// be used and won't accept any configuration other than the one used here. Trying to use a
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// different pin configuration will result in a compiler error.
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let sck = gpioa.pa5.into_af5(&mut gpioa.moder, &mut gpioa.afrl); |
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let miso = gpioa.pa6.into_af5(&mut gpioa.moder, &mut gpioa.afrl); |
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let mosi = gpioa.pa7.into_af5(&mut gpioa.moder, &mut gpioa.afrl); |
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let mut spi = Spi::spi1( |
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p.SPI1, |
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(sck, miso, mosi), |
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SPI_MODE, |
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4.mhz(), |
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clocks, |
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&mut rcc.apb2, |
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); |
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// // Setup of the needed pins is finished here
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// // Now the "real" usage of the eink-waveshare-rs crate begins
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let mut epd = EPD1in54::new(&mut spi, cs, busy, dc, rst, &mut delay).unwrap(); |
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// Clear the full screen
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epd.clear_frame(&mut spi).unwrap(); |
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epd.display_frame(&mut spi).unwrap(); |
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// Speeddemo
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let small_buffer = [Color::Black.get_byte_value(), 16 as u8 / 8 * 16 as u8]; |
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let number_of_runs = 100; |
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for i in 0..number_of_runs { |
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let offset = i * 8 % 150; |
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epd.update_partial_frame(&mut spi, &small_buffer, 25 + offset, 25 + offset, 16, 16).unwrap(); |
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epd.display_frame(&mut spi).unwrap(); |
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} |
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// Clear the full screen
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epd.clear_frame(&mut spi).unwrap(); |
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epd.display_frame(&mut spi).unwrap(); |
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// Draw some squares
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let mut small_buffer = [Color::Black.get_byte_value(), 160 as u8 / 8 * 160 as u8]; |
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epd.update_partial_frame(&mut spi, &small_buffer, 20, 20, 160, 160).unwrap(); |
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small_buffer = [Color::White.get_byte_value(), 80 as u8 / 8 * 80 as u8]; |
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epd.update_partial_frame(&mut spi, &small_buffer, 60, 60, 80, 80).unwrap(); |
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small_buffer = [Color::Black.get_byte_value(), 8]; |
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epd.update_partial_frame(&mut spi, &small_buffer, 96, 96, 8, 8).unwrap(); |
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// Display updated frame
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epd.display_frame(&mut spi).unwrap(); |
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// Set the EPD to sleep
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epd.sleep(&mut spi).unwrap(); |
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loop {} |
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} |
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//exception!(HardFault, hard_fault);
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#[exception] |
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fn HardFault(ef: &ExceptionFrame) -> ! { |
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panic!("{:#?}", ef); |
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} |
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//exception!(*, default_handler);
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#[exception] |
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fn DefaultHandler(irqn: i16) { |
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panic!("Unhandled exception (IRQn = {})", irqn); |
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} |
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